A Study on Scheduling Algorithms for Reconfigurable Computing
In recent days, FPGAs, otherwise known as Field Programmable Gate arrays are employed in every vertical of application involving digital systems. Especially in the areas of Networking, Embedded systems and on a broader spectrum, FPGAs are useful in Internet of Things as well. The reconfigurable nature of FPGAs along with low power, and high speed execution of digital logic makes them the preferred choice in every domain. The operating system plays a major role in controlling the CPU and the FPGA, which is employed as an accelerator, in any digital system for an efficient control of the applications. While assigning tasks to FPGAs, preemptive scheduling can not be employed as it is very difficult to stop the execution of an algorithm in hardware and store the intermediate results of different registers of the module. The conventional scheduling algorithms used for software applications such as FCFS, SJF, priority scheduling can be modified to suit the needs of FPGAs. Hence, in this paper, a comparative study of the scheduling algorithms when the processes are routed to FPGA architecture for execution is presented.A comparative study of the scheduling algorithms in this context has led to an inference that the overall performance has seen a significant improvement with respect to allocating the hardware tasks to FPGAs and minimizes the waiting time.