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Meenakshi J, Divya V, Nilanjan Tewari. Switching Methodology using Selective Harmonic Elimination for a Nine Level Transistor Clamped Cascaded Inverter. DE [Internet]. 2021Nov.29 [cited 2024Apr.30];:455 -466. Available from: http://www.thedesignengineering.com/index.php/DE/article/view/6972