Novel 1t-1d Single Ended Sram Cell Concept Using Finfet Technology for Low Power Applications

Abstract

There is a growing demand for high-density integrated circuits on a very large scale today (VLSI). The key problem is SRAM cell consistency due to the scaling of the CMOS technology. Also, the market for VLSI low-power circuits is indeed very high at the moment. The key component of cache and memory caching (MC) in SRAM tends to be very stable as most programs access reliable information repeatedly. The major challenge in SRAM cells is balancing power and delay. CMOS-based SRAM cells face issues such as less reliability, high cost, and large variation in parameters. Also, the gate in CMOS devices starts to lose its control over the channel. Due to this reason FinFET based SRAM cells are recommended over CMOS. FinFETs are emerging devices that can be used to enhance the SRAM design performance at lower technology nodes. This study illustrates the design of 1T-1D SRAM cell design in both CMOS, FinFET technologies. This work aims to reduce the leakage of power without affecting the SRAM cell logic state. The cell structure is simple to design also makes it exceptionally accessible and cost-effective. The minimum number of transistors in a 1T-1D cell reduces the total area. Tanner EDA working platform of 7nm FinFET technology is used to implement the proposed 1T-1D SRAM cell. This work achieved low power up to 99% and an improvement in delay reduction upto 98%.