Implementation of FIR Filters by Using Area and Power Efficient Approximate Multiplier

  • M. Shiva Rohith Reddy, M. Revanth Sai Kumar, P. V. N. Sai Ganesh, Mr. Swaminadhan Rajula

Abstract

Approximate computing technique in which the resource requirement is minimal in contrast to exact counterpart by facilitating the reduction of power and area. Efficiency is achieved by tolerating the error. Tolerance of the error to a level it is acceptable relays on application. Applications like image processing and signal processing withstand computational errors by achieving efficiency in power or area. Error that is involved facilitates to reduction in the Area/power and the cost. However, there is trade-off between computational error and power/area. The proposed multiplier is highly efficient with acceptable computational error. Approximate multiplier is designed using Dadda multiplier technique. Performance of the proposed multipliers is examined on the Signal processing application, in which the proposed design achieves the efficient power and area in comparison to exact counterpart.

Published
2021-11-29
How to Cite
M. Shiva Rohith Reddy, M. Revanth Sai Kumar, P. V. N. Sai Ganesh, Mr. Swaminadhan Rajula. (2021). Implementation of FIR Filters by Using Area and Power Efficient Approximate Multiplier. Design Engineering, 428 - 437. Retrieved from http://www.thedesignengineering.com/index.php/DE/article/view/6969
Section
Articles