Design and Implementation of Higher Performance Decimal Compressors Using Multiplexer Based Approach

Abstract

Nowadays, Data transmission has become more critical because of the size of the data. Decimal compressors are a technique for accumulating partial products during multiplication and decimal addition, as well as for reducing data size. Binary full adders and code conversions are used to implement decimal compressors, resulting in high-speed operation. Because the combination of weights of 10–15 causes an overflow, decimal codes are employed in such a manner that the weight of each 4-bit decimal adds up to just 9.For the sum of weights up to 9, we use the family of codes 3321, 5211, 4221, etc, and all the combinations in this family are suitable for decimal arithmetic operations. In this project, we designed an efficient 13:2 decimal compressor by using a vertical bit array compressor with the use of a digit recorder. Multiplexer-based compressors have been used to design 11:2 decimal and 13:2 decimal compressors. By proposed method will reduce the vertical computation time along with less area (2853.26SQU). With the proposed model the DC power consumption (1.3006 µ-watt) will reduces a lot. By the proposed method the rate at which the data getting across output also reduces,i.e., speed will increase in computation time, and delay(13.130ns) will reduces. In order to reduce the size of the data and secure it, the digit recorder is implemented in hardware by converting 4221 to 5211 codes. This is done using delay-optimized compressor methods. These are commonly used to analyze various performance parameters, including latency, power, and area. The architecture is validated using Xilinx ISE Design Suite 14.7 and the Synopsys DC Compiler.