Design of Sigmoid Architecture for Deep Learning Hardware Accelerators
Abstract
Deep learning architectures are significantly evolved during the recent decades. Over this time, DL-based neural networks gained momentum in diverged applications including portable consumer electronics. In AI-based mobile applications such as wearable biomedical devices, IoT, etc., the dedicated DL architectures are essential to perform the feature extraction and classification efficiently with low power. In DL architectures, the activation module plays a crucial role in determining the output from a neuron. In this paper, a hardware module is proposed to perform the sigmoid function suitable for DL-based hardware accelerators. The proposed 8-bit sigmoid module has shown the maximum SQNR of 70.97dB and the maximum relative error of 0.6156%.