Phase Noise Analysis and Design of Low Leakage FinFET Ring Oscillator with Adaptive Body Biasing

Abstract

Phase Noise Margin in An adaptive leakage power minimization based FinFET ring oscillator for energy harvesting applications of implantable bio-medical devices has been presented in this paper. An adaptive body biasing based leakage power minimization optimizes the leakage power consumption of the implantable bio-medical device since they are battery operated devices. The desired frequency of oscillation has been achieved by five stage ring oscillator whose frequency is 1 KHz. The proposed ring oscillator has been designed and phase noise is analyzed using 20nm FinFET technology and it has been simulated in Cadence Virtuoso Analog Design Environment (ADE) using Spectre as the simulator. The supply voltage of the proposed ring oscillator is kept at 50mV to minimize the dynamic power and leakage power consumption. The proposed ring oscillator consumes very less dynamic power of 41.98 nW compared to the existing CMOS ring oscillator which consumes 50 µW. The leakage power consumption of the proposed ring oscillator is 4.25 pW. The proposed low leakage ring oscillator outperforms well and it is more suitable for low power implantable bio-medical devices. The Phase noise of the proposed ring oscillator is -156.5 dBc/Hz @ 1000 Hz offset frequency and simulation temperature is 27◦C compared to the existing CMOS ring oscillator which is