Design and Performance Evaluation of Power Optimized Pipeline A/D Converter

Abstract

In very large scale integrated (VLSI) design, a challenge is to optimize the power without compromising the speed in an analog and mixed mode signal circuit. This research work is carried out to design a 12-bit Pipeline A/D converter (ADC) of 400MS/s sampling rate to meet the low power applications. The design is focused to determine low power, speed and resolution in pipeline ADC to cater different applications. The main advantages of pipeline method are simple to implement, more flexible to optimize the power and makes layout design simple. A proposed technique holds sample and hold circuit (S/H), multiplying DAC, comparator and operational transconductance amplifier (OTA) to design the pipeline ADC architecture. OTA is used to convert differential input voltage into current with the help of a switched capacitor integrator module. A dedicated sample-and-hold amplifier (SHA) is eliminated due to addition of sample-and-hold circuit in the initial stage of Pipeline ADC. Obtained results shows integral and differential non-linear values are +0.61/-0.75LSB and +0.48/-0.55LSB respectively. From simulation the value of Signal to noise dynamic range (SNDR) achieved is 64.2dB and 81.8dB of spurious free dynamic range (SFDR) is plotted. An EDA platform with cadence tool is used to design, simulate and verified the proposed design on 45nm gpdk library.