Review Analysis on Faster Energy Efficient Adiabatic FA topologies for certain Low power Applications

Abstract

The emergence and extensive use of hand-held appliances and their huge demand have drawn people's attention to the power-saving plan of these battery-powered regimes. The Arithmetic and logic unit is the core of the multimedia mainframe built into the compact electronic device. Consequently, the low-power realization of the Full adder (FA) module, which is a central component of the arithmetic structure, can ominously reduce the total power of the system. Adiabatic logic is one and only the most eminent methods for degrading energy dissipation in circuits with high switching movement. Payable to problem of scaling in MOS devices, carbon nanotube field effect transistors (CNFETs) have been set up as the most promising alternatives to current Field Effect Transistor devices. In this review article, several hybrid cell Full adder topologies on non-adiabatic logic and adiabatic logic and number of transistors count are discussed. The simulation is performed under different environments, such as different supply voltages, load capacitance and operating frequencies that may arise under actual conditions. In this review article, the 4-Bit Ripple Carry adder is analyzed for feature research work in the adiabatic and non-adiabatic families for a more complete analysis.