ULTRA LOW POWER AND OPTIMIZED HIGH SPEED DFT IMPLEMENTATION FOR ASIC SOC

Abstract

In this research work, introduced an ultra-low power DFT architecture for MIMO-OFDM applications. In present era 4G and 5G communication technologies are facing many power and performance issues with DFT processors, various radix such as 8/16/32 based optimization algorithms are applied to achieve variable length of 4k/8k points. These technologies are normal in operation and consume more power. Therefore, an advanced DFT design is necessary, so in this work "S-BOX” and Parallelism novel technique is used to improve the performance and power consumption. The proposed S-BOX model can reduce the number of multiplication operation and parallelism improves the operational speed. The entire implementation is designed and verified on Cadence-allegro-17.2, where simulation, synthesis, floor planning and power analyzers are realized with the help of cadence calculator design. 8-point s-box DFT occupies 105.15 um2 area and consumes power of 7mW and attains the throughput of 59.33GBPS. Moreover 16-point s-box DFT occupies 123.35um2 area and consumes power of 9mW and attains the throughput of 57.33GBPS. Also 32-point s-box DFT occupies 132.35um2 area and consumes power of 10.24 mW and attains the throughput of 56.45GBPS This design is more useful for telecommunication applications through MIMO in 5G technology. The optimized radix 8 s-box DFT improve the performance than present architectures.