Area Efficient and Low Power Floating-Point FFT Processor for Next Generation Wireless Communication systems

Abstract

Fast Fourier Transform (FFT) processor having a significant impact on communication systems has been an interesting topic for researchers during the last decade.  This Processor is designed using pipelined fused floating-point operations on complex data using IEEE std.754 format.  FFT architecture uses a three-stage pipe-lined butterfly structure using pipelined fused floating-point units (FFPU) and multiplexers to get the desired low power and area efficient processor.  We use 1GHz clock with gate count of ∼729K.  It exhibits signal-to-quantization noise ratio (SQNR) of 138.9 dB, power consumption equals to 605.65mW and a core area of 1.61 mm² (1.27mm × 1.27mm) with an execution time of 7.49µs for a 4096-point FFT processor. However, there is an increase in latency with the increase in the size of FFT. The FFT Processor is implemented using 90nm CMOS technology.