HYBRID LP-DSDT DATA MOMEORY IMPLEMENTATION ON ROUTER ARCHITECTURE IN PACKET TRANSFER APPLICATIONS

Abstract

Building such a high-speed router would raise many technological problems, one of them being the packet buffer design, mainly because in router design it is important to provide worst-case bandwidth guarantees and not just average-case optimizations. A previous packet buffer design provides worst-case bandwidth guarantees by using a hybrid SRAM/DRAM approach. Next-generation routers need to support hundreds of interfaces (i.e., ports and service classes). Unfortunately, high bandwidth for hundreds of interfaces requires the previous design to use large SRAMs which become a bandwidth bottleneck. The key observation we make is that the SRAM size is proportional to the DRAM access time but we can reduce the effective DRAM access time by overlapping multiple accesses to different banks, allowing us to reduce the SRAM size. The key challenge is that to keep the worst-case bandwidth guarantees, we need to guarantee that there are no bank conflicts while the accesses are in flight. We guarantee bank conflicts by reordering the DRAM requests using a modern issue-queue-like mechanism. Because our design may lead to fragmentation of memory across packet buffer queues, we propose to share the DRAM space among multiple queues by renaming the queue slots. Also such packet access and its implementation would be implemented with respect to the design structure as to provide better scenario on the router structure utilizing the LP-DSDR memory. Current implementation on DSDT referring to dual stream dual transfer of the data on each port any router architecture. This technique would provide a specific scenario for reduction of the gates and other logics improving the power related problems.