DESIGN RELIABILITY SIGN OFF FOR MODERN SoC CLOSURE

Abstract

Modern SOC cycles are severely constrained in every aspect of design, turnaround time for design verification cycle, time to market. With each lower process node, the pre silicon reliability validation of the SOC design is getting more and more into the critical mode. Every attempt is made for improving quality, turnaround time and overall time to market of the SoC. One such attempt is in the qualification and validation of the industry standard reliability validation flow and their accuracy in reporting potential si issues upfront. While sign off design flows generally follow pessimistic trend of reporting violations compared to the Si outcome, the same pessimism adds to false violation reporting and increases sign off reliability checks closure in terms of man hours and quality of SOC design sign off closure.