DESIGN AND ANALYSIS OF IN-TOLERANT APPROXIMATE FULL ADDERS FOR APPROXIMATE COMPUTING
Abstract
As the design complexity of the VSLI circuit’s increases day by day which results in the enormous increase of power dissipation, cost and also vulnerable to process variation. Hence which can be reduced by adopting approximate computing techniques. Which can be widely used in applications like multimedia and signal processing applications where approximate output is allowable. In this paper, we have been proposed a novel approximate full-adder for such imprecision-tolerant applications. The obtained Experimental results clearly indicate the proposed circuit withstand over a wide range of process variations and also consumes less power respectively.