Heuristic Approach on Probabilistic Model for Implementing Power Reduction Using Adiabatic Circuits for Memory Logics

Abstract

The design model and its functional elements which improvises on incremental change in transistor based on the clock-frequency lead to reduce the power as the requirement to be. The design on the low power implicates on one of the adiabatic scenario for each set of CMOS circuitry utilized which implicates on the design circuitry that have to be implemented. Our design aims to initiate a low power design with 4 bit proposed HPM (Heuristic Probability Model) with D-FF and 4 bit T-FF latency factor utilizing the effective probability model which ensures the correct design parameters. These parametric criteria would suggest the design of the Flip flop would be based on the clock gating procedure to reduce the power associated with 4 bit-FF with 32 bit wide FIFO with TRNG circuit, SDRAM memory and 4-bit memory cell implemented with using Xilinx-vivado-2019 and Microwind tool ensuring the reduced power in systolic model with addressing data. Our design improves more than 10% of power reduction with use of glitch reduction circuit for 4 bit D-FF and T-FF designed when compared to existing design. This design circuit aims to improvise a Verilog model for FIFO, latch-FF glitch model for each set of the operation characteristics on FIFO model for random number generation. Hence, we emphasize these models to be utilized with each performance characteristics ensuring better accuracy.