FINFET Based 13t Low Power SRAM
The decrease in chip size and increase in chip density escalate the complexity in designing high performance and low power consuming system on a chip. To increase the battery life of portable devices and to reduce the leakage and dynamic power are the primary goals of the VLSI circuit design. The size of the MOSFET cannot be decreased beyond a limit and its flat structure is inefficient which leads to the emergence of FINFET at sizes of 30nm and below. Multi-gate FINFET supersedes 2D MOSFET because it has better controlling over short channel effect due to its dual gate structure. This paper includes the design of static random access memory (SRAM) using multi-gate FINFET. The performance analysis of 13TSRAM and 11TSRAM is compared at nano-scale technology node(18nm) and the results are obtained using Cadence Virtuoso simulation toll version 6.1. The proposed full custom model aims at optimized power and delay. This FINFET based 13T SRAM cell increases efficiency of power by the use of gating technique and reduces delay by the use of transmission gates.