Performance Analysis of Clock Gating Designs in Low Power Vlsi Circuits

  • CH HARITHA, M DEVANATHAN
Keywords: : Low power VLSI,RTL,Clock Gating, EDA, LEF, LIB

Abstract

Power utilization is a significant bottleneck of system performance and it is recorded as one of the main three difficulties in International Technology Roadmap. By and by, an enormous part of the on-chip power is devoured by the clock system which is made of the clock distribution network and flip flops. In this paper, different plan procedures for a low power clocking system are overviewed. Among them clock gating is a successful method to lessen dynamic force scattering, by eliminating the clock signal when the circuit isn't being used. Clock gating will reduce the clock power by trimming the clock tree along with including some new logic into the circuit.We noticed clock gating which diminishes the overall power by around 75%. A 75.12% decrease of clock driving power (Dynamic power) and 6.4% decrease of leakage power is accomplished.

Published
2021-05-31
How to Cite
CH HARITHA, M DEVANATHAN. (2021). Performance Analysis of Clock Gating Designs in Low Power Vlsi Circuits. Design Engineering, 1304 -. Retrieved from http://www.thedesignengineering.com/index.php/DE/article/view/1810
Section
Articles