Area and Delay Analysis of Hardware Implementation of Floating Point based 8-Point FFT

Abstract

The complex multipliers in mathematics seems to be need of the hour and a very important aspect. The application used as a complex operationwith respect to the real and imaginary numbers together. In many of the practical aspect the design substantiated to be anaiding hand for co-functionality units. The results show that proposed FFT consumes very less resources in terms of slices, flip flops and multipliers to provide cost effective solution for DSP applications.The hardware realization of fast fourier transform(FFT) consists of complex arithmetic operations such as multiplyand accumulate. The key idea of this paper is to implement the8-point Radix-2 DIT (Decimation In Time) FFT. In the FFTalgorithm the twiddle factor generation by traditional method ofgenerating sine and cos is replaced by having the twiddle factor stored in the ROM for 8 point DITFFT. For the multiply and accumulate unit the Single precision floating point multiplier is used. The adder/substractor blocks usedin the implementation of DITFFT are floating point adder and substractor.The FFT implementation using single precision floating point number with and without pipeling(FIFO) are performed .The area and delay are obtained and analyzed for with and without pipelining(FIFO) of the 8-point DITFFT calculation.