Implementation of High speed and Low Area FIR Filter for Wireless Communications

  • Alluri Navaneetha, Kalagadda Bikshalu

Abstract

This paper presents high speed and low area 4th order FIR filter using BZFAD multiplier technique. To increase the speed and reduce the area of the FIR filter different multiplication techniques such as Add and shift multiplier and BZFAD (Bypass zero feed A directly) multipliertechniques are designed and implemented on Spartan 6 XC6SLX45 FPGA using structural level modeling of Verilog HDL and the total on chip power is found in Vivado 2014. Multiplieranalysis isdone as it is main building block of FIR filter design. Comparison of FIR filter with multiplier is donewith existing one as it is important block in digital signal processor which requires high speed and low area.The FIR filter consists of three basic modules which are adder, delay and multiplier block.

The performance of the FIR filter is largely influenced by the multiplier which slowest block out of all.

Published
2021-05-18
How to Cite
Alluri Navaneetha, Kalagadda Bikshalu. (2021). Implementation of High speed and Low Area FIR Filter for Wireless Communications. Design Engineering, 989 - 1001. Retrieved from http://www.thedesignengineering.com/index.php/DE/article/view/1633
Section
Articles